Integrated circuits after being fabricated and packaged are typically tested on certain types of prior art automatic test equipment ("ATE") before being shipped to customers. Devices not passing certain tests are typically discarded and not shipped. One type of ATE system includes a test head that includes a socket that holds a device under test ("DUT"). The ATE can also be used to simply learn the characteristics of the particular DUT.
FIG. 1 illustrates the pin electronics 1 and DUT socket 6 of a test head of one prior art ATE. Circuitry identical to pin electronics 1 is included for each pin of DUT 4 plugged into socket 6. Pin electronics 1 is used to transfer signals between the rest of the ATE and pin 8 of DUT 4.
Pin electronics 1 includes a driver 7 for sending signals to pin 8 of DUT 4 over interconnect path 5. Pin electronics 1 also includes a valid logic low comparator 3 and a valid logic high comparator 2 coupled to path 5 for receiving signals from DUT 4. Comparator 2 is coupled to a reference high voltage, also referred to as a preset high voltage. Comparator 3 is coupled to a reference low voltage, also referred to as a preset low voltage. Comparators 2 and 3 allow the ATE to sense whether pin 8 of DUT 4 is providing a valid logic high and a valid logic low signal, respectively.
Interconnect path 5 acts like a bidirectional transmission line with a characteristic impedance Zo.
One prior art DUT 4 is a high-speed complementary metal oxide semiconductor ("CMOS") integrated circuit ("IC"). The rise and fall times of the outputs of the CMOS DUT 4 are typically less than or equal to the time it takes the output signals of CMOS DUT 4 to travel from a pin of DUT 4 to comparators 2 and 3. In addition, the effective output impedance of the CMOS DUT 4 is typically much lower than the impedance Zo of interconnect path 5. Furthermore, the impedance of driver 7 in an off state is quite high and the impedances of the inputs of comparators 2 and 3 are also quite high.
The above-mentioned timing and impedance characteristics associated with CMOS DUT 4 and pin electronics 1 contribute to the observed result that an output voltage transition on pin 8 of a CMOS DUT 4 connected to pin electronics 1 results in multiple reflections on interconnect path 5 between the output pin of DUT 4 and (1) driver 7 and (2) comparators 2 and 3. These multiple reflections are referred to as ringing on interconnect path 5, or simply as ringing.
FIG. 2 is a Shmoo plot of one example of what ringing on interconnect path 5 might look like. FIG. 2 shows a plot 47 of what the voltage measured at low comparator 3 (or high comparator 2) versus time might look like when there is a high to low voltage transition on pin 8 of DUT 4. Plot 47 illustrates what the multiple reflections that comprise ringing might look like.
Ringing can result in inaccurate readings by the ATE of the timing and output voltage characteristics of DUT 4. For example, if comparators 2 and 3 of FIG. 1 are strobed while ringing is occurring on interconnect path 5, the voltage sensed by comparators 2 and 3 might not be the true quiescent output voltage of pin 8 of DUT 4. The ringing on interconnect path 5 may raise (or lower) the voltage seen by comparators 2 and 3 relative to the true output voltage of pin 8 of DUT 4. The ATE could accordingly erroneously conclude, for example, that DUT 4 is a defective device, even though in reality DUT 4 is not defective.
FIG. 3 illustrates pin electronics 40 and DUT socket 6 of another typical prior art ATE. Circuitry identical to pin electronics 40 is included for each pin of DUT 4 plugged into socket 6.
Pin electronics 40 includes an interconnect path 29 between DUT socket 6 and driver 7, comparators 2 and 3, and diode bridge 30. Diode bridge circuit 30 includes diodes 33 through 36. Bridge circuit 30 acts as a load circuit for interconnect path 29. Bridge circuit 30 includes a current source input I.sub.SCR, a current sink output I.sub.SNK, and a reference voltage terminal V.sub.REF.
Pin electronics 40 includes DC parametric measurement circuitry 44 coupled to interconnect path 29 via line 32 and switch 48. Pin electronics 40 also includes time calibration circuitry 42 coupled to interconnect path 29 via line 31 and switch 49.
Pin electronics 40 also includes switch 46 that can be used to disconnect driver 7, comparators 2 and 3, and diode bridge 30 from DUT 4.
Pin electronics 40 includes clamping diodes 41 and 42 to provide protection against overvoltages and undervoltages. Diode 41 is coupled to voltage V.sub.MAX, which is the maximum voltage that the pin electronics can sustain without being damaged. Diode 43 is coupled to voltage V.sub.MIN, which is the minimum voltage that the pin electronics can sustain without being damaged. V.sub.MAX is typically approximately two volts greater than the driver 7 maximum voltage V.sub.DVH and typically approximately two volts less than the driver 7 minimum voltage V.sub.DVL. Therefore, diodes 41 and 43 are typically reverse biased with driver 7 operating within its limits of V.sub.DVH to V.sub.DVL.
For prior art pin electronics 40, impedance matching is performed with respect to interconnect path 29 and DUT 4. On the circuit board containing pin electronics 40, pad sizes and lead lengths are adjusted so that there is impedance matching. Typically, interconnect path 29 is comprised of segments that give an equivalent overall impedance of 50 ohms over a large bandwidth approaching one gigahertz.
Although for prior art pin electronics 40 the location of clamping diodes 41 and 43 is not crucial, for one prior art ATE, clamping diodes 41 and 43 are nevertheless connected to interconnect path 29 at a point near to the inputs to comparators 2 and 3 and far from pin 8.
Prior pin electronics 40 also suffers the effects of ringing on interconnect path 29.
One prior approach to solving the problem of ringing is to allow a certain period of time to pass before enabling comparators 2 and 3 of FIGS. 1 and 3 with strobes. This time delay allows the ringing on interconnect paths 5 and 29 to dampen out before comparators 2 and 3 are enabled.
One disadvantage of this time delay approach is that it typically delays the time at which comparators 2 and 3 can be sampled, which sometimes prevents the testing of certain output states of DUT 4 at the specified time of the test specification for DUT 4. The time period of significant ringing to dampen to about 20% can typically range from (1) about 15 transit times (through interconnect paths 5 or 29) when the DUT 4 output impedance is approximately 10 ohms and the impedance of interconnect path 5 or 29 is about 50 ohms to (2) about five transit times (through interconnect paths 5 or 29) when the DUT 4 output impedance is about 30 ohms and the impedance of interconnect path 5 or 29 is about 50 ohms.
Another prior approach to solving the ringing problem is to set the threshold voltages of comparators 2 and 3 outside of the range of voltages induced by ringing.
One disadvantage of this threshold voltage approach is that it sometimes prevents testing DUT 4 to the test specification with respect to certain voltage levels.
Another prior approach to solving the ringing problem is to attempt to match the output impedance of pin 8 of DUT 4 with the impedance of interconnect path 5 or 29 by adding a resistor (not shown) in series with output pin 8 of DUT 4. Interconnect path 5 or 29 is thus connected to output pin 8 of DUT 4 via the resistor.
Adding a resistor in series with pin 8 and line 5 or 29 has certain disadvantages, however. To begin with, a true output impedance match cannot always be achieved as a practical matter given that impedances vary from pin to pin and from DUT to DUT. Even if the proper series resistor is inserted, the use of that series resistor typically reduces the direct current ("DC") test accuracy given the voltage drop across the series resistor. Moreover, the series resistor typically degrades test timing accuracy given that the series resistor typically introduces additional time delay that varies and thus typically cannot be accurately adjusted for thorough calibration. Furthermore, if DUT 4 includes generic pins that perform both input and output functions, then a series resistor connected to those pins would typically degrade a signal applied by driver 7 to those generic pins. Ringing is associated with outputs from the DUT, not with inputs to the DUT. The use of a series resistor in interconnect path 5 or 29 would, however, affect input signals applied to DUT 4.
Another prior approach to solving the ringing problem is to terminate interconnect path 5 or 29 in its characteristic impedance at the driver 7 side by turning driver 7 on when comparators 2 and 3 are in operation, thereby allowing driver 7 to act as a voltage source with a resistance, for example, of 50 ohms.
One disadvantage associated with this prior approach is that when driver 7 is turned on, driver 7 can add a DC current load to the output circuit of DUT 4, depending upon the voltage that driver 7 is set to. This can sometimes cause excessive power to be dissipated in the output circuit of DUT 4, which in turn, may sometimes damage the DUT or sometimes result in inaccurate test results.